If a Generic Interrupt Controller (GIC) implements 64 priority levels, which priority field bits hold the priority value?
A. bits [5:0]
B. bits [7:2]
C. bits [15:10]
D. bits [31:26]
正解:B
質問 2:
In general, when programming in C, stack accesses will be reduced by:
A. Configuring the compiler to optimize for space.
B. Never passing more than four parameters in function calls.
C. Disabling inlining.
D. Declaring automatic variables as "packed".
正解:B
質問 3:
When applied to locations in memory configured using a write-back cache strategy, what does a data cache 'clean' operation do?
A. Speculatively preloads data into the cache
B. Writes dirty data cache lines to memory and marks those lines as invalid
C. Reloads dirty data cache lines from memory
D. Writes dirty data cache lines to memory
正解:D
質問 4:
In the VFPv4-D32 architecture, which of the following best describes the arrangement of the registers?
A. D0 overlaps with S0, D1 with S1 etc. up to D31 and S31
B. D0..D31 and S0..S31 are separate register banks
C. D0..D31 overlap with S0..S63
D. D0..D15 overlap with S0..S31, and D16..D31 do not overlap with any single-precision registers
正解:D
質問 5:
Which of the following is an accurate description of network storage as compared to on-chip RAM?
A. It has lower capacity
B. It is always available
C. It is easy to share with other devices
D. It is quicker to access
正解:C
質問 6:
According to the AAPCS (with soft floating point linkage), when the caller "func" calls sprintf, where is the value of the parameter "x" placed?
#include <stdio.h>
void func(double x, int i , char *buffer)
{
sprintf(buffer, "pass %d: value = %f\n", i, x); }
A. 8 bytes on the stack
B. Split between registers R3 and R4
C. VFP Register D0
D. Split between register R3 and 4 bytes on the stack
正解:A
質問 7:
Which of these processors is only available as a single core configuration?
A. Cortex-A15
B. Cortex-A5
C. Cortex-A9
D. Cortex-A8
正解:D
Takeda -
こちらの問題集から、9割以上出ました。大変助かりました。やはり信頼できる商品です。