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質問 1：
When using a Generic Interrupt Controller (GIC), how does code cause a software-generated interrupt?
A. By writing to the F bit in the CPSR
B. By executing an SGI instruction
C. By writing to a register in the GIC
D. By writing to the I bit in the CPSR
正解：C
質問 2：
In which of the following situations would you use a mutex to avoid synchronization problems?
A. A single-threaded application needs to manage two separate UART peripherals
B. In a dual-core system, processor A needs to access UART A and processor B needs to access UART B
C. In a dual-core system, a UART is accessed by a single thread running on one of the processors
D. Two independent threads running on a single processor both need to access a single UART
正解：D
質問 3：
Which of the following techniques can be used to obtain a precise count of clock cycles when profiling software over an arbitrarily long period of time using the Performance Monitoring Unit?
A. Use of the divide-by 64 counting option to avoid an overflow of the cycle counter
B. Modification of the application software being profiled, to insert timestamps at regular intervals
C. A dedicated real-time clock to provide the total cycle count
D. Use of the overflow interrupts, to extend the range of the built-in 32-bit counter
正解：D
質問 4：
A Programmer's View CPU model usually provides:
A. Cycle-accurate simulation of the cache and memory system.
B. Instruction-accurate simulation of the CPU.
C. Cycle-accurate simulation of the CPU.
D. Simulation of user-defined memory-mapped peripherals.
正解：B
質問 5：
The interval of time from an external interrupt request signal being raised to the first fetch of an instruction of the interrupt handler is called the interrupt:
A. Jitter
B. Service thread
C. Priority
D. Latency
正解：D
質問 6：
Which one of these statements is TRUE about code running on final hardware without a debugger attached?
A. Exception handlers must execute from ROM or flash memory
B. RAM must be initialized before reset
C. It must not execute semihosting SVC or BKPT instructions
D. It must start executing from RAM
正解：C
質問 7：
For Cortex-A series cores, what instruction(s) are recommended to implement a mutex or semaphore?
A. DMB
B. DSB and ISB
C. SWP and SWPB
D. LDREX and STREX
正解：D
When using a Generic Interrupt Controller (GIC), how does code cause a software-generated interrupt?
A. By writing to the F bit in the CPSR
B. By executing an SGI instruction
C. By writing to a register in the GIC
D. By writing to the I bit in the CPSR
正解：C
質問 2：
In which of the following situations would you use a mutex to avoid synchronization problems?
A. A single-threaded application needs to manage two separate UART peripherals
B. In a dual-core system, processor A needs to access UART A and processor B needs to access UART B
C. In a dual-core system, a UART is accessed by a single thread running on one of the processors
D. Two independent threads running on a single processor both need to access a single UART
正解：D
質問 3：
Which of the following techniques can be used to obtain a precise count of clock cycles when profiling software over an arbitrarily long period of time using the Performance Monitoring Unit?
A. Use of the divide-by 64 counting option to avoid an overflow of the cycle counter
B. Modification of the application software being profiled, to insert timestamps at regular intervals
C. A dedicated real-time clock to provide the total cycle count
D. Use of the overflow interrupts, to extend the range of the built-in 32-bit counter
正解：D
質問 4：
A Programmer's View CPU model usually provides:
A. Cycle-accurate simulation of the cache and memory system.
B. Instruction-accurate simulation of the CPU.
C. Cycle-accurate simulation of the CPU.
D. Simulation of user-defined memory-mapped peripherals.
正解：B
質問 5：
The interval of time from an external interrupt request signal being raised to the first fetch of an instruction of the interrupt handler is called the interrupt:
A. Jitter
B. Service thread
C. Priority
D. Latency
正解：D
質問 6：
Which one of these statements is TRUE about code running on final hardware without a debugger attached?
A. Exception handlers must execute from ROM or flash memory
B. RAM must be initialized before reset
C. It must not execute semihosting SVC or BKPT instructions
D. It must start executing from RAM
正解：C
質問 7：
For Cortex-A series cores, what instruction(s) are recommended to implement a mutex or semaphore?
A. DMB
B. DSB and ISB
C. SWP and SWPB
D. LDREX and STREX
正解：D
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