最新なARM EN0-001問題集（210題）、真実試験の問題を全部にカバー！

質問 1：
In a symmetric multi-processing (SMP) software architecture, which of the following pairs of statements are TRUE? (Select the option in which BOTH statements are TRUE).
A. The roles of individual cores are determined dynamically. Each core has its own set of external peripherals.
B. The roles of individual cores are statically determined by the system designer. Hardware must be implemented to provide cache coherency between the cores.
C. Each core has the same view of memory and shared peripherals. Any user application, process or task can be scheduled to run on any core.
D. Each core has the same view of memory and peripherals. The roles of individual cores are statically determined by the system designer.
正解：C

質問 2：
Which of these C99 keywords can be used to indicate that two arrays do not overlap?
A. "pure"
B. "restrict"
C. "volatile"
D. "static"
正解：B

質問 3：
Processors which implement the ARMv7-A architecture can be configured to allow unaligned memory access. Unaligned accesses have a number of advantages, disadvantages, and limitations.
Which TWO of the following statements are true? (Choose two)
A. A program compiled using unaligned accesses can be safely executed on all ARMv7-A devices
B. Unaligned accesses can only be made to Normal memory
C. If the relevant control register setting is enabled all loads and stores can function from unaligned addresses
D. Unaligned accesses may take more cycles to execute than aligned accesses
E. Unaligned loads and stores are necessary for accessing fields in packed structures
正解：B,D

質問 4：
Literal pool loads to access constants at run-time can be minimized by:
A. Storing the code in ROM.
B. Using Thumb code rather than ARM code.
C. Ensuring constants can be encoded as immediates in the current instruction set.
D. Compiling and linking as position-independent code.
正解：C

質問 5：
Which of the following processors includes a Generic Interrupt Controller as a standard component?
A. Cortex-A9 MPCore
B. Cortex-R4F
C. Cortex-M3
D. Cortex-A8
正解：A

質問 6：
Using a Generic Interrupt Controller (GIC), when the interrupt handler writes to the End of Interrupt Register (ICCEOIR), which of the following state transitions might occur for that interrupt ID?
A. Inactive to Active
B. Active to Pending
C. Active to Inactive
D. Pending to Active
正解：C

質問 7：
Which one of these statements is TRUE about code running on final hardware without a debugger attached?
A. Exception handlers must execute from ROM or flash memory
B. RAM must be initialized before reset
C. It must not execute semihosting SVC or BKPT instructions
D. It must start executing from RAM
正解：C